A typical computer system includes a number of peripheral devices (hereinafter often referred to as "peripherals" or "devices") that provide mass storage for the system and allow communication outside the system. These peripherals include disk drives, tape drives, terminals, and the like. However, the peripherals typically operate on a time scale that is at least an order of magnitude slower than the operation of other functional units within the system. While it is a known practice to interface peripheral controllers directly to a main system bus, this typically requires a large amount of overhead associated with each peripheral controller. Accordingly, it is a known practice to couple the peripheral controllers to a peripheral sub-bus, and to provide an intelligent I/O channel processor (hereinafter "IOCP") for controlling communication between the sub-bus and the main system bus. To simplify terminology, the peripheral sub-bus will often be referred to simply as the "bus." Directions on the bus will be designated relative to the IOCP, with terms such as "transmit" and "outbound" referring to communications from the IOCP and terms such as "receive" and "inbound" referring to communications to the IOCP.
Once a bus has been dedicated to the peripheral devices, it becomes a major concern that the bus resources be fully utilized and allocated among the various peripherals in manner that permits reasonable bus access to all the peripherals. The prior art has utilized a number of schemes in attempts to divide up the bus resources. The simplest prior art scheme effects a sequential allocation wherein each requesting device is assigned complete use of the bus and allowed to complete its data transfer at the maximum bus rate or maximum device rate, whichever is slower, prior to relinquishing the bus to the next requesting device. The next step up in complexity involves prioritizing specific devices or grouping bus traffic by direction in cases of physically long buses where turnaround times are large. More sophisticated prior art systems implement a form of time sharing which allocates time slots to requesting devices. Such systems suffer from the problem that a given device may be evicted at the end of a time slot, even if it has not completed its transfer, thus requiring that a transfer continue in some future time slot. While the transfer will eventually be completed, such eviction imposes unreasonable limitations on the effective device speed.
While an addressing scheme is a necessary feature of any bus system, considerable care must be taken to make sure that such a scheme does not unduly increase the bus cost or decrease the bus speed. Generally, addresses are responsible for identification of the data destination, including both the specific device as well as the actual data location within it. The most common prior art system adds separate address lines to the bus and assigns them to the addressing function. This adds to the cost of the bus medium but offers the ability to select individual addresses for each bus operation.
Other systems transmit address information on the data bus in a time shared manner. This typically requires extensive control to ensure that the additional burden on the data section does not slow the entire bus down. One way of minimizing the burden imposed by having to time share the data bus is to require that once a group of bus cycles is allocated to an address, the entire transfer be completed on subsequent cycles. However, this tends to freeze out short transfers while the long ones are being completed. Moreover, where the device speed is slow relative to the bus, the bus is prevented from running at its own (faster) rate.
An additional set of complications arise when attempts are made to operate a bus bi-directionally. Data buses are characterized as to whether they can transfer data in one direction (simplex), in both directions at different times (half duplex), or in both directions simultaneously (full duplex). True full duplex operation is obtainable only with two separate data paths, one for each direction, and requires two sets of control lines. The alternative, a single bi-directional data path that is controlled in such a fashion as to seem full in nature, requires the control system to handle multiple interleaved operations in different directions in such a manner as to make them appear simultaneous. However, for buses with this ability to interleave operations, time sharing becomes increasingly complicated as the address information also needs to be interleaved.
Thus, attempts to render flexible and efficient the allocation of bus resources have been met with undesirable increases in overhead.